This application is based on and claims priority on Japanese Patent application No. 2001-178974, filed on Jun. 13, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device including a pad of damascene structure and a method of manufacturing the same.
2. Description of the Related Art
The design rules for semiconductor devices become more intricate as the integration density thereof increases. A technical limit is appearing in the methodology, wherein after a surface metallic wiring layer of aluminum, wolfram(tungsten), or the like is deposited on a surface of an insulating layer, a resist pattern is formed on the surface metallic wiring layer and then the wiring layer is directly etched.
In place of the methodology patterning the surface wiring layer by etching, a damascene process is increasingly used to embed wiring material in wiring grooves and via holes formed by an etching process in a beforehand prepared inter-level insulating layer. The damascene process is suitable to form a narrow wiring layer surrounded by silicon oxide layers.
Aluminum primarily used as wiring material in the prior art is limited with respect to resistance and electro-migration. Thanks to low resistance and a higher limit for the electro-migration, copper is increasingly being used. It is difficult to pattern a copper layer by etching. However, copper wiring can be formed by a damascene process.
The known damascene processes include a single step damascene process to form a via conductor and a wiring pattern conductor, respectively, in different processes and a dual step damascene process in which a via hole and a wiring groove are first formed and a via conductor and a wiring pattern conductor are formed therein in another step.
A semiconductor integrated circuit device includes pads on its surface for connection thereof to another device. Since wiring is formed by the damascene process, the pad is formed also by the damascene process today.
Referring to FIGS. 6A to 6H, description will be given of a method of forming a single-damascene pad in the prior art. When copper is used as wiring material, for preventing oxidation of an underlying wiring layer in the etching of a photo resist pattern, it is necessary to use an etching stopper layer of silicon nitride (SiN) or the like, having an anti-oxidation function and an etching stopper function. An example of processes of manufacturing a pad section will be described by referring to the drawings.
As shown in FIG. 6A, a lower insulating layer d1 is first formed on a lower wiring w1, via holes are formed in the lower insulating layer d1, and a lower via conductor v1 is formed in each via hole.
The lower via conductor v1 can be formed, for example, by plating a copper layer on a whole surface of an underlying structure and then conducting chemical and mechanical polishing (CMP) process on the plated surface.
As shown in FIG. 6B, an etching stopper layer (sp) is formed with a silicon nitride (SiN) layer of 70-nanometer (nm) thickness on the lower insulating layer d1 to cover the lower via conductors (v1). An insulating layer (dp) composed of, for example, a silicon oxide film of 2000-nm thickness is formed on the etching stopper layer (sp). When it is desired that the insulating layer has a low dielectric constant, silicon oxide including fluorine, porous silicon oxide, or the like is used.
The etching stopper layer (sp) and the insulating layer (dp) collectively have a function of an inter-level insulating film. However, the etching stopper (s)p is a layer for preventing oxidation of the via conductors (v1) and of an etching stopper in the etching of the insulating layer (dp), and the insulating layer (dp) primarily serves as an inter-level insulating film.
The dielectric constant of the etching stopper layer (sp) is higher than that of the insulting layer (dp). By increasing the thickness of the etching stopper layer (sp), the etching stopper function and the oxidation preventive function can be improved. However, this increases capacitance between the wiring layers and hence hinders a high-speed operation of the semiconductor device. Therefore, the thickness of the etching stopper layer (sp) is desirably reduced to a necessary minimum value.
As shown in FIG. 6C, a photo resist pattern (PR) is formed on the insulating layer (dp) to define an opening for a pad. The pad opening is defined such that a surface of the lower via conductor (v1) below the pad opening is exposed.
As shown in FIG. 6D, the insulating layer (dp) is etched using the photo resist pattern (PR) as an etching mask. By using, for example, a parallel plate plasma etching system, the layer (dp) is etched by dry etching in an atmosphere including C4F8 as a main etching gas. The etching proceeds faster in a peripheral region of the opening than in a central region thereof. As a result of the difference in the etching rate, an etching retardation region (RT) in a central region (or a sub-trench (ST) in an edge section of the opening) is formed.
The sub-trench indicates a contour formed by the etching rate difference between the wiring edge region and the wiring central region in the etching of a groove for wiring having a large width. Since the etching rate is higher in the wiring edge region than in the wiring central region, a contour of a groove appears in edge region. The central region becomes higher in level than the edge region.
FIG. 7A is a graph showing an example of a relationship between the etching rate of the wiring edge region and the wiring central region. The abscissa represents the wiring width in micrometers (xcexcm) and the ordinate represents the etching rate in nanometers per minute (nm/min). As shown in FIG. 7A, while the etching rate is almost fixed in the wiring edge region regardless of the change in the wiring width, the etching rate in the wiring central region has a tendency to become lower as the wiring width increases.
For example, when the wiring width is 30 xcexcm, the etching rate in the wiring edge region is about 380 nm/min and that in the central region is about 300 nm/min.
In the etching of a silicon oxide layer of about 2000-nm thickness, the etching rate is 380 nm/min in the wiring edge region, and hence 5.26 minutes are required for the complete etching of a wiring edge region. In contrast therewith, since the etching rate of the wiring central region is 300 nm/min, a silicon oxide layer of 422-nm thickness still remains when the wiring edge region is just or completely etched.
As shown in FIG. 6E, when the etching is stopped in a state in which the sub-trench (ST) appearing in the pad edge section reaches the etch stopper (sp), i.e. the insulating layer (dp) is just etched, the central portion of the insulating layer (dp) remains as a remaining pattern (dpx). Then, the via conductors (v1) below the pattern (dpx) will not be exposed.
When over-etching is performed to etch the silicon oxide layer completely, the etching stopper layer at the edge region is disadvantageously etched. Assume that deviation of the etching rate in a wafer is about 10%. Then, the period of time necessary to etch the silicon oxide film (2200-nm thickness in the wiring central region) is 6.7 minutes.
The 6.7-minute etching time corresponds to the etching of a silicon oxide film of about 2787-nm thickness in the wiring edge region. This results in an over-etching thickness of 787 nm. Assume that a selection ratio between the silicon oxide film and the etching stopper layer is ten. Then, the etching stopper layer is etched up to a depth or thickness of 78.7 nm. If the etching stopper layer has a thickness of 70 nm, the etching stopper layer is completely etched and hence vanishes in the wiring edge region.
As shown in FIG. 6F, when the insulating layer (dp) of the pad central section is completely etched by the over-etching, etching of the sub-trench region (ST) further proceeds in the pad peripheral section and the etching stopper layer (sp) vanishes.
When the etching continues in the state in which the lower via conductors (v1) is exposed, copper of the conductors (v1) directly comes into contact with the etching gas (particularly, with fluorine in the gas) as shown in FIG. 6G.
When the via conductors of copper is exposed after the etching stopper zone vanishes, copper fluoride (CP) is produced on surfaces of the via conductors, for example, in a fluorine atmosphere of the etching gas.
Furthermore, copper oxide is produced on surfaces of the conductors of copper exposed by a subsequent resist etching process in an oxygen atmosphere.
As shown in FIG. 6H, when the etching continues, top portions of the via conductors vanish in the pad peripheral section. The via conductors are retarded, respectively, in the via holes. When empty spaces (L) appear, respectively, in the upper portions of the via holes, it becomes difficult to embed an upper wiring layer in the via holes.
When this phenomenon takes place, a contact error may take place. As previously discussed, when it is desired to form an opening having a large area in an insulating layer, subsequent processes are adversely influenced by occurrence of the phenomenon of the sub-trench.
When it is desired to form a wide pad groove in a two-layer inter-level insulating layer including an etching stopper layer and an insulating layer in the single damascene process, the etching rate difference between the pad central section and the pad peripheral section easily causes insufficient contact between the pad conductor and the via hole conductor. A need therefore exists for a technique to efficiently form a wide pad groove having a large area.
It is therefore an object of the present invention to provide a pad capable of preventing the insufficient contact thereof to the lower wiring layer.
According to one aspect the present invention, there is provided a semiconductor device, comprising a semiconductor substrate including semiconductor elements, an underlying wiring layer formed over said semiconductor substrate, said underlying wiring layer including a wiring pattern; an underlying insulating layer formed on said semiconductor substrate, said underlying insulating layer covering said underlying wiring layer; a plurality of via holes extending through said underlying insulating layer and reaching said underlying wiring layer; a plurality of via conductors embedded respectively in said via holes; an insulating stack layer formed on said underlying insulating layer, said insulating stack layer covering said via conductors, said insulating stack layer including a first insulating layer having an etching characteristic and a second insulating layer having an etching characteristic different from that of said first insulating layer; a pad groove formed through said insulating stack layer, said pad groove defining a pad region in which said via conductors are exposed, said pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in said pad groove.
According to another aspect the present invention, there is provided a semiconductor device manufacturing method, comprising the steps of (a) forming pad lower conductor structure over a semiconductor substrate, said pad lower layer conductor structure comprising an underlying layer and lower via conductors embedded in said lower insulating layer, (b) forming an insulating stack layer on said pad lower layer conductor structure, said insulating stack layer including a first insulating layer having an etching characteristic and a second insulating layer having an etching characteristic different from that of said first insulating layer, (c) forming an etching mask on said insulating stack layer, said etching mask defining a pad region and a remaining pattern in the vicinity of said lower via conductor in said pad region, (d) etching said insulating stack layer using said etching mask as a mask and forming a pad groove in which said lower via conductors are exposed, and (e) embedding a pad conductor in said pad groove.
Also, when a wiring layer is again formed as a re-wiring layer on a pad once completely formed, a technique similar to the technique previously described can be employed.
In the etching process, polymer is deposited while the etching is being conducted. When a large amount of polymer is deposited, the etching rate decreases. When a small amount of polymer is deposited, the etching rate increases.
FIG. 7B simply shows a state of a groove pattern edge section. Assuming that a solid angle at a point on a bottom surface of the edge section is xcexa9a, wherein the solid angle is schematically defined using the point on the bottom surface and two upper points defined by a photo resist pattern or the like as shown in FIG. 7B.
As shown in FIG. 7C, assuming that a solid angle at a point on a bottom surface of the groove pattern central section is xcexa9b, wherein the solid angle is schematically defined using the point on the bottom surface and upper points defined by a photo resist pattern or the like, as shown in FIG. 7C. As can be seen from FIGS. 7B and 7C, the solid angle xcexa9a is less than the solid angle xcexa9b.
Assume, for example, the groove has a depth of 1 (part) and a width of 2 (parts). The solid angle from an edge section of the groove is about 63xc2x0 and that from a central section of the groove is about 90xc2x0.
In the groove central section with the larger solid angle, a large amount of polymer is deposited and the etching rate decreases.
In contrast therewith, in each groove edge section with the smaller solid angle, a small amount of polymer is deposited and the etching rate increases.
FIG. 7D is a graph schematically showing a relationship between the solid angle and the etching rate. The graph qualitatively shows a phenomenon in which the etching rate decreases, when the solid angle from a point of a surface being etched increases.
By adjusting the contour of the mask to form a remaining or residual pattern of the insulating film in the pad region, a desired etching speed can be guaranteed in the etching of a region having a large area. Therefore, favorable electric contact can be established at least in a region of the pad to be brought into contact with the lower conductor.
Even when the sub-trench phenomenon occurs, the insufficient contact with the lower conductor layer can be prevented.